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With its HyperScale hierarchical methodology, the 2015.12 PrimeTime release reduces the need for expensive compute assets. "Synopsys PrimeTime's continuously improving performance helps us meet our demanding signoff schedules." "As a supplier of world-class computing solutions, our design teams must ensure our highly integrated semiconductor products achieve timing closure across a wide range of scenarios," said Bruce Fishbein, vice president of NCD IC engineering at Cavium. Finally, tighter correlation of graph-based analysis (GBA) to path-based analysis (PBA), achieved through parametric on-chip variation (POCV) technology, means designers can spend less time doing runtime-costly PBA analysis to eliminate false violations. Second, PrimeTime provides improved scaling across 16 cores for 10-15X faster throughput compared to single core runs. The latest release of PrimeTime takes a three-pronged approach to smarter and faster timing closure: First, it boosts performance, beginning with 2X overall faster run time and a 10X boost in reporting function speed. System-on-chip (SoC) designers face pressure to close timing quickly, including reducing runtimes and finding necessary high-end compute resources.
#SYNOPSYS PRIMETIME UPGRADE#
"The 2015.12 release of PrimeTime keeps our customers well ahead of the curve, providing significant reduction in turnaround time without requiring them to upgrade existing hardware." "In anticipation of designers' future timing closure challenges, Synopsys continues to offer smarter, more efficient technology," said Robert Hoogenstryd, senior director of marketing for design analysis and signoff tools at Synopsys.
#SYNOPSYS PRIMETIME SOFTWARE#
This software release helps ensure chip designers can meet demanding signoff schedules at advanced process nodes. New PrimeTime technology significantly improves turnaround time (TAT) and power reduction, while providing smarter utilization of compute resources.
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(Nasdaq: SNPS) today announced that the 2015.12 release of the PrimeTime ® static timing analysis tool provides major enhancements to address the challenges of timing and power closure for FinFET designs. Advanced Engineering Change Order (ECO) technology enables power reductions of up to 40 percent.HyperScale technology proven to save schedule time and compute resources in more than 25 tapeouts.2X speedup, 16 core scalability and reduced need for costly path-based analysis (PBA) reporting significantly improves turnaround time (TAT).